The present invention relates to memory storage systems and devices.
This invention relates generally to memory systems, and more particularly to memory systems which include a memory buffer that serves as an interface between a host controller and memory devices or other memory buffering devices residing on a DIMM, the memory buffer being optionally located on the DIMM itself or as part of the motherboard on which the DIMM connectors are also located.
Traditional computer systems, such as servers, workstations, desktops and laptops, all use pluggable memory which can be inserted into slots on the computer's motherboard as needed. The most common form of pluggable memory is the Dual In-line Memory Module (DIMM). Historically, DIMMs contain multiple RAM chips—typically DRAM—each of which has a data bus width of 4 or 8 bits. Typically, eight or nine 8-bit DRAM chips (or twice as many 4-bit DRAM chips) are arranged in parallel to provide each DIMM with a total data bus width of 64 or 72 bits; the data bus, typically referred to as the ‘DQ’ bus, is connected to a host controller. Each arrangement of 64 or 72 data bits using DRAM chips in parallel is termed a ‘rank’.
A command/address (CA) bus also runs between the host memory controller and each DIMM; the CA and DQ busses together form a ‘system’ bus. With a basic unbuffered DIMM, the CA bus is connected to every DRAM on the DIMM. As a result, there is a high electrical load on the CA bus, given by the product of the number of DRAMs times the number of ranks. For the DQ bus, the number of electrical loads is equal to the number of ranks.
A buffering device is employed to reduce loading in a ‘load reduction’ DIMM (LR-DIMM). An LR-DIMM containing multiple DRAM chips uses a logic device to buffer the DQ and CA signals between the DRAMs and a host controller. The logic device may be, for example, a single device such as the iMB (isolating Memory Buffer) from Inphi Corporation. Memory systems of this sort are described, for example, in co-pending U.S. patent application Ser. Nos. 12/267,355 and 12/563,308, which are incorporated herein by reference, for all purposes. Further details of conventional techniques can be found in U.S. Pat. No. 8,966,327, commonly assigned, in the name of Dr. David Wang, which issued Feb. 24, 2015, and hereby incorporated by reference for all purposes.